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I 2 C
Table 44. I 2 C AC electrical specifications (continued)
All values refer to V IH (min) and V IL (max) levels (see Table 43 ).
Parameter
Fall time of both SDA and SCL signals
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device (including
Symbol 1
t I2CF
t I2PVKH
t I2KHDX
V NL
Min
20 + 0.1 C B4
0.6
1.3
0.1 × OV DD
Max
300
—
—
—
Unit
ns
μ s
μ s
V
hysteresis)
Noise margin at the HIGH level for each connected device (including
V NH
0.2 × OV DD
—
V
hysteresis)
Notes:
1. The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t I2DVKH symbolizes I 2 C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the t I2C clock reference (K) going to the high
(H) state or setup time. Also, t I2SXKL symbolizes I 2 C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the t I2C clock reference (K) going to the low (L) state or hold time. Also, t I2PVKH symbolizes I 2 C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t I2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. MPC8309 provides a hold time of at least 300 ns for the SDA signal (referred to the V IH (min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum t I2DVKL has only to be met if the device does not stretch the LOW period (t I2CL ) of the SCL signal.
4. C B = capacitance of one bus line in pF.
The following figure provides the AC test load for the I 2 C.
Output
Z 0 = 50 Ω
R L = 50 Ω
OV DD /2
Figure 32. I 2 C AC test load
The following figure shows the AC timing diagram for the I 2 C bus.
SDA
t I2CF
t I2CL
t I2DVKH
t I2SXKL
t I2KHKL
t I2CR
t I2CF
SCL
t I2SXKL
t I2CH
t I2SVKH
t I2PVKH
S
t I2DXKL
Sr
P
S
Figure 33. I C bus AC timing diagram
2
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
43
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